FPGA Based Classic HP Core

[bkn42]

Over in this thread I mentioned a FPGA design I did which implemented a Classic HP calculator's (HP-35, HP-45, HP55,...) hardware. I promised in the thread I'll explain my design in more detail in this forum. So, here is an introduction to my FPGA project:

After lurking here for a long time, I got interested in how HP designed the insides of their early calculators. I researched sites like this one (specifically: HP Calculator Opcode Map), Jacques Laporte site (great info on how the HP-35 calculator works), and Eric Smith's nonpareil HP calculator site (and others I'm forgetting). I though it would be fun to design a FPGA core from scratch that would be functionally equivalent to a classic HP "CPU" -- yes, I think things like this are fun (even after doing FPGA/ASIC design work for a living for the past 15 years).

I did the design in VHDL and targeted a Xilinx Spartan 3 FPGA device. It took about 4 months, last year, to finish (I only worked on it during my fleeting spare time).

This is the hardware I used:

• FPGA Hobby Board: I used the Papilio FPGA Platform - specifically a Papilio One 250K development board. This board uses has a Xilinx Spartan 3E FPGA chip (a XC3S250E) - not the biggest FPGA but its inexpensive and has plenty of resources for this project.
• 16 Digit Seven Segment LED Display: This display uses a Titan Micro TM1640 IC. I bought mine from DealExtreme but do a Google search for "TM1640 LED Board" and you will find many suppliers. This is a great display board for a DIY calculator but it is not pocket-calculator-size -- more like desktop-calculator-size. It has a simple to use I2C like interface.
• PS/2 Keyboard: You know, the standard PC keyboards before USB versions took over.
  

So, the LED display was my output, the PS/2 was input (in place of a keypad) and the FPGA board did all the "magic".
Here is a picture of the setup:
   
Sorry, its not the best picture; I'll try and get better pictures soon. (I hope the picture shows up in the post -- it does not show in the preview.)

Some of other notes:

• The FPGA Classic HP Core I designed is functional the same as the original calculators (I hope). The FPGA Classic HP Core directly executes the 10-bit op-codes of the original calculators. Do not confuse this with emulating the op-codes (like what the many SW emulators do) -- there is no embedded CPU (i.e. ARM, AVR, MicroBlaze,...) in the design -- there is no SW program running to interpret the HP 10-bit op-codes.
• I know of the 41CL project (and the 41CL is a real project compared to the "toy" I created). I did not use 41CL design code is a reference -- I wanted the "fun" of designing on my own. Anyway the 41CL project is done in Verilog -- I only speak VHDL.
  

The FPGA Classic HP Core (FCHPC) does the actual 10-bit op-code execution. And, there is logic wrapped around the FCHPC that deals with the LED display and the PS/2 keyboard interface. Obviously, the LED display and keyboard are not the same as the original HP hardware and I had to come up with a way to connect modern I/O devices to the FCHPC.
Here is a list of features of the FCHPC:

• Functionally equivalent to the original HP Calculator "CPU". This means it will execute the original, unchanged, ROM images of the HP-35, HP-45, HP-55,...
• Not timing equivalent to the original HP Calculator "CPU". This means it does not execute the 10-bit opcodes in the same time as the original calculators. The FCHPC executes each op-code in far fewer clock cycles. (Plus, in a modern FPGA the FCHPC can run at much higher clock rates then the original calculators.)
• Written in VHDL and tested in a Xilinx Spartan 3 FPGA. Targeting other FPGAs should not be an issue. I avoided using Xilinx FPGA specific features and using Xilinx's CoreGen tool -- logic is inferred from VHDL as much as possible. (Warning: That last statement requires some knowledge of FPGA designing; don't worry if it made no sense to you.)
  

Here are the features of the logic wrapped around the FCHPC:

• LED Display driver: Converts the FCHPC current X value into a displayable form. This is different than the original calculator which had to drive the segments of its LED display directly. I used a I2C LED display. The FCHPC has two output ports: the X register (internal to the FCHPC, this is the A register) and the mask register (internally, this is the B register). Using the X and mask registers, the formated LED display output is created.
• Keyboard Interface: Converts PS/2 serial keyboard scan codes to HP keypad scan codes. This conversion is different for each type of HP calculator.
• Internal clock generation: Creates the clock that all FPGA logic will use. In this design it is a multiple of 7MHz (currently 28MHz). The reason for 7MHz is its easy to derive a throttling signal for the FCHPC to slow the op-code execution to match a real HP-55. This allows the HP-55's timer mode to be accurate.
• Two speed modes are available: 1) real mode - the FCHPC executes op-codes at the same rate as an HP-55 and 2) turbo mode - the FCHPC executes op-codes at full speed. The speed of the turbo mode depends on the internal FPGA clock. Currently, at 28MHz, turbo mode is about 1600 times faster than the original HP-55! The speed mode is selected by special keys on the PS/2 keyboard.
• There are some extra display features supported that did not exist on the original calculators:
  • Indicators for the shift keys. For example, a "F" or "G" is displayed on the far right of the LED display for the HP-55 version when a shift is active.
  • Indicator for the speed mode. This shown in the far right decimal point.
  • Instead of a flashing display for an error condition, the message "-- Error --" is displayed (non-flashing). The original flashing display for an error could not be used in the FPGA version. The flashing was done in the calculator's micro-code (i.e. a SW delay loop). In turbo mode, the flashing would be too fast to see!
    

In a future posts, I'll dig into the details of the FCHPC and the outer logic that handles the I/O. I'm not sure how much detail people want to see -- I could easily get into serious nerdy digital design stuff and this could bore anyone without FPGA/ASIC design experience.
Please, post your comments/questions and I'll tailor my future posts accordingly.

And, yes, I plan to make available the VHDL source code on github. I'm working on adding and cleaning up comments in the code, now. I'll upload the project to github soon and I'll post when its available.

I now realize I'm a better digital designer than a tech writer; so, I hope this post was not too disjointed or rambling.

Brian