An attempt to standarize HP-41 Bank Switching.

[Diego Diaz]

Hi all,

After some e-mail converasion held on May past year and including Ángel Martín, Monte Darymple, Sylvain Côté and myself about the latest Bank Switched ROMs developed by Ángel and the way they were handled both in the 41CL and Clonix/NoVs, it was clear that the single BS used in my modules doesn't cope with the needs of keeping track of the selected bank on every page/port.

At this point, the most appropriate BS method was the one implemented in the 41CL which invloved port dependent BS.

At first it looks like a simple modification to include page dependent BS in the NoV's module firmware, so I made the required changes and they went to the latest revision as of Oct. 16 2020.

Regrettably, this page dependent BS scheme proven to cause problems when dealing with the Advantage module and its Bank Switched upper page, as reported some weeks ago for a NoV-64d user.

After a long and fruitful phone call with Ángel last week, it seemed that the best compromise to handle both the "old style" 2 banks BS in the Advantage and the new 4 banks used in the most recent modules will be to keep page dependent BS on pages #0-#7 and change pages #8-#F to port dependent BS.

If I've understood it right, this is the way the 41CL is handling ist BS (Monte can correct me otherwise).

I've built new firmware including this feature for the NoV-64(d), both in the HEPAX-1D and 1H+LIBRARY4 versions and have done some preliminary tests. However the number of possible combinations of modules and/or peripherals is way too large for me to test them all.

So I'd appreciate your help in testing these changes with the configuration of your preference before updating the firmware archive or include this changes in the rest of the modules.

Please contact me by PM or mail and I'll send the relevant files.

Thanks a lot for your support and best wishes from the Canary Islands (AKA: Caronte's doorstep lately )

Diego.

[Ángel Martin]

Volcanoes apart, hope things are great over there. Sounds to me it's the correct approach, let us know when you're done with the implementation.

Cheers,
ÁM

[MeindertKuipers]

It is really good to have some kind of standardization. I recall that there was a table published in another thread (cannot find it now) with all variations of BS implementations.
This may be important for the DM41X and MLDL2000 platforms. I am a bit hesitant to change the implementation in the MLDL2000 (port based BS in ALL pages, including 0-7). Will do some testing with LIB4 in the lower pages in the MLDL2000.

[Sylvain Cote]

(09-30-2021 02:49 PM)MeindertKuipers Wrote:  I recall that there was a table published in another thread (cannot find it now) with all variations of BS implementations.

HP-41C Bank Switching Schemes [2020-03-25] ?
I still need to add the missing devices (W&W+DM41X) and I will have to update Clonix/NoV implementation.

[Sylvain Cote]

Meindert,
Can you please validate my next update for MLDL2000.
Thank you!
Sylvain

MLDL2000 packaged in a card reader shell:

• Unit specifications:
  • released in June 2005
  • SRAM: 1M x 16 bits (s/n < 2050)
  • SRAM: 512K x 16 bits (s/n >= 2050)
  • Flash: 1M x 16 bits (Flash can contain up to 255 ROM images)
  • firmware < v1.51: support bank switching from page 0x6 to page 0xF
  • firmware >= v1.51: support bank switching from page 0x0 to page 0xF
    
• Bank switching instructions:
  • ENBANKx/ENROMx 1 to 4 are supported (0x100, 0x180, 0x140, 0x1C0)
    
• Bank switching behavior:
  • even/odd port pages are linked (0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
  • even/odd system pages are linked (0x0/0x1, 0x2/0x3, 0x4/0x5, 0x6/0x7)
  • PWO event clears bank switching state
    

[MeindertKuipers]

We seriously need a LIKE button here in the forum

(09-30-2021 02:57 PM)Sylvain Cote Wrote:  

(09-30-2021 02:49 PM)MeindertKuipers Wrote:  I recall that there was a table published in another thread (cannot find it now) with all variations of BS implementations.

HP-41C Bank Switching Schemes [2020-03-25] ?
I still need to add the missing devices (W&W+DM41X) and I will have to update Clonix/NoV implementation.

[MeindertKuipers]

Will do, please have a bit of patience since I have many parallel activities at the moment (most non-calculator related)

(09-30-2021 03:32 PM)Sylvain Cote Wrote:  Meindert,
Can you please validate my next update for MLDL2000.
Thank you!
Sylvain

MLDL2000 packaged in a card reader shell:

• Unit specifications:
  • released in June 2005
  • SRAM: 1M x 16 bits (s/n < 2050)
  • SRAM: 512K x 16 bits (s/n >= 2050)
  • Flash: 1M x 16 bits (Flash can contain up to 255 ROM images)
  • firmware < v1.51: support bank switching from page 0x6 to page 0xF
  • firmware >= v1.51: support bank switching from page 0x0 to page 0xF
    
• Bank switching instructions:
  • ENBANKx/ENROMx 1 to 4 are supported (0x100, 0x180, 0x140, 0x1C0)
    
• Bank switching behavior:
  • even/odd port pages are linked (0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
  • even/odd system pages are linked (0x0/0x1, 0x2/0x3, 0x4/0x5, 0x6/0x7)
  • PWO event clears bank switching state
    

[Diego Diaz]

Hi all,

Thanks for the input!

Very helpful and detailed (as usual) information in your article Sylvain. :-)

I'm not planning to modify the earlier 32K type modules: Clonix-41, NoVRAM & NoV32.

Current preliminary mods are available for the NoV-64(d) using HEPAX (1D or 1H).

If they proven to be functional will be migrated to Clonix-D, USB-41 and non-HEPAX NoV-64(d).

Will keep on testing.

Best wishes.

Diego.