Threaded Mode | Linear Mode

Ángel Martin · (This post was last modified: 07-23-2017 08:03 AM by Ángel Martin.)

Hi Sylvain, thanks for reporting this issue. There were indeed two typos in the module that caused the problem: (1) a bad go-to address, and (2) wrong XROM id# in the bank-switched page.

I've corrected those two, and also took the opportunity to add a call to [NFRPU] to terminate some other functions that were not updating the LCD on completion (due to the RTN stack depletion).

Try the attached ROM files and let me know how it fares.

Cheers,
ÁM

Sylvain Cote · (This post was last modified: 07-23-2017 09:18 PM by Sylvain Cote.)

Hello Angel,

Thanks!

I am using the following setup on a 41CL (updated to: 2017-06-28) and on a HP-41CX with a Clonix-D module.

Code:

loaded WARPB1   at 0x830 mapped to page 8 bank 0  YCRC=0xD3E28A93  Rev:2017-07-23

loaded WARPB2   at 0x831 mapped to page 8 bank 1  YCRC=0x7705223D  Rev:2017-07-23

using  LIBRARY4 at 0x120 mapped to page 4 bank 0  YCRC=0xBF465233  Rev:2017-05-16

using  YFNX-2C  at 0x00A mapped to page F bank 0  YCRC=0x99BDA28B  Rev:2017-06-19 (CL only)

With the Clonix-D/HP-41CX everything went ok and the previous two issues has been resolved.

With the 41CL I am at lost here, it seems this is the first time for me that I am trying to plug bank-switched module from RAM.
I have tried the following ...
a) "4LIB 4" PPLUG "-830 8" PPLUG
b) "4LIB 4" PPLUG "+830 8" PPLUG
c) "4LIB 4" PPLUG "*830 8" PPLUG
each time the CL freeze big time and it take 30 minutes to get around it.
The 41CL Extreme Functions manual is no help here for me, I have read it several time but I do not see the pattern I need to do this.

Sylvain

Monte Dalrymple · 07-24-2017, 12:53 AM

(07-23-2017 09:10 PM)Sylvain Cote Wrote: Hello Angel,

Thanks!

I am using the following setup on a 41CL (updated to: 2017-06-28) and on a HP-41CX with a Clonix-D module.

Code:

loaded WARPB1 at 0x830 mapped to page 8 bank 0 YCRC=0xD3E28A93 Rev:2017-07-23 loaded WARPB2 at 0x831 mapped to page 8 bank 1 YCRC=0x7705223D Rev:2017-07-23 using LIBRARY4 at 0x120 mapped to page 4 bank 0 YCRC=0xBF465233 Rev:2017-05-16 using YFNX-2C at 0x00A mapped to page F bank 0 YCRC=0x99BDA28B Rev:2017-06-19 (CL only)

With the Clonix-D/HP-41CX everything went ok and the previous two issues has been resolved.

With the 41CL I am at lost here, it seems this is the first time for me that I am trying to plug bank-switched module from RAM.
I have tried the following ...
a) "4LIB 4" PPLUG "-830 8" PPLUG
b) "4LIB 4" PPLUG "+830 8" PPLUG
c) "4LIB 4" PPLUG "*830 8" PPLUG
each time the CL freeze big time and it take 30 minutes to get around it.
The 41CL Extreme Functions manual is no help here for me, I have read it several time but I do not see the pattern I need to do this.

Sylvain

The "*830 8" PPLUG should work. Perhaps there is something with the order
of modules in the Ports? I have YFNX in 8, YFNF in 9 and YUPS in F when I plug
4LIB into 4 and then *850 into C (I first copied the previous version of WARP to
850-853). Everything works okay with this setup.

Ángel Martin · (This post was last modified: 07-24-2017 07:15 AM by Ángel Martin.)

(07-24-2017 12:53 AM)Monte Dalrymple Wrote: [quote='Sylvain Cote' pid='76465' dateline='1500844245']

With the 41CL I am at lost here, it seems this is the first time for me that I am trying to plug bank-switched module from RAM.
I have tried the following ...
a) "4LIB 4" PPLUG "-830 8" PPLUG
b) "4LIB 4" PPLUG "+830 8" PPLUG
c) "4LIB 4" PPLUG "*830 8" PPLUG
each time the CL freeze big time and it take 30 minutes to get around it.
The 41CL Extreme Functions manual is no help here for me, I have read it several time but I do not see the pattern I need to do this.

Hi Sylvain,

the WARP_CORE only has two banks, but regardless of that the syntax is the same as for all bank-switched modules irrespective of the number of banks:

PLUG *ADR PG$

where ADR is the RAM address of the main bank, and PG$ is the hex page#
the asterisk is the key for the CL to know this is a bank-switched configuration.

The banks are expected to be loaded at 0xADR for the main bank, and 0x(ADR+1) for the second bank. This is no different from how it works in flash, where the WARP ROMS are loaded at 0x1B8 and 0x1B9..

Hope this helps, shout if you still have issues..

Sylvain Cote · (This post was last modified: 07-25-2017 01:24 PM by Sylvain Cote.)

Hello Monte & Ángel,

Thank you for your support, it is now working.

Here is what I did ...

MMUDIS
MMUCLR
SERINI
BAUD48
"YFNX"
PLUG4U
TURBO50
MMUEN
"830000-0FFF"
YIMP // File: WARPB1.ROM YCRC=0xD3E28A93 Rev:2017-07-23
"830"
YCRC -> D3E28A93
"831000-0FFF"
YIMP // File: WARPB2.ROM YCRC=0x7705223D Rev:2017-07-23
"831"
YCRC -> 7705223D
"4LIB 4"
PPLUG
"*830 8"
PPLUG

Two times (maybe more) I wrongly entered "-4LIB 4" instead of "4LIB 4" and the CL never gave me any input error.
I assume that upon activation of "*830 8" without the 4LIB mapped or with something else mapped the result was unexpected.

Best regards,

Sylvain

edit: typo

Monte Dalrymple · 07-25-2017, 03:18 AM

(07-25-2017 03:06 AM)Sylvain Cote Wrote: Two times (maybe more) I wrongly entered "-4LIB 4" instead of "4LIB 4" and the CL never gave me any input error.
I assume that upon activation of "*830 8" without the 4LIB mapped or with something else mapped the result was unexpected.

Best regards,

Sylvain

PPLUG doesn't check the ALPHA length. I just looks at the 6 least-significant digits,
and ignores digit 7 (the "-"). So it actually did plug in the 4LIB.

Monte

Sylvain Cote · (This post was last modified: 07-25-2017 02:50 PM by Sylvain Cote.)

Hello Monte,

I have created the following scenarios to clear up my (non?) understanding of the port assignment using PPLUG.
Please do the correction where they are needed.

Example 1 : one set of applications spent over 2 non-bank-switched images that will normally use one port on the back

location: the 2 images are at 0x840 and 0x841
expected: 0x840 at page 8 bank 0 & 0x841 at page 9 bank 0
command: "+840 8" PPLUG

Example 2 : one set of applications spent over 4 non-bank-switched images that will normally use two ports on the back

location: the 4 images are at 0x840, 0x841, 0x842 and 0x843
expected: 0x840 at page 8 bank 0, 0x841 at page 9 bank 0, 0x842 at page A bank 0 & 0x843 at page B bank 0
command: "%840 8" PPLUG

Example 3 : one set of applications spent over 2 bank-switched images that will normally use one half-port on the back

location: the 2 images are at 0x840, 0x841
expected: 0x840 at page 8 bank 0 & 0x841 at page 8 bank 1
command: "*840 8" PPLUG

Example 4 : one set of applications spent over 4 bank-switched images that will normally use one half-port on the back

location: the 4 images are at 0x840, 0x841, 0x842 and 0x843
expected: 0x840 at page 8 bank 0, 0x841 at page 8 bank 1, 0x842 at page 8 bank 2 & 0x843 at page 8 bank 3
command: "*840 8" PPLUG

Example 5 : two sets of applications spent over 7 bank-switched images that will normally use one port on the back

location 1: the app 1 has 3 images are at 0x840, 0x841 and 0x842
location 2: the app 2 has 4 images are at 0x843, 0x844, 0x845 and 0x846
expected 1: 0x840 at page 8 bank 0, 0x841 at page 8 bank 1 & 0x842 at page 8 bank 2
expected 2: 0x843 at page 9 bank 0, 0x844 at page 9 bank 1, 0x845 at page 9 bank 2 & 0x846 at page 9 bank 3
is it ?
command 1: "*840 8" PPLUG
command 2: "*843 9" PPLUG
or
command: "/840 8" PPLUG

Question for #5: how do you find how many images are part of the same image set ?

Thank you!

Best regards,

Sylvain

Monte Dalrymple · 07-25-2017, 05:11 PM

(07-25-2017 02:47 PM)Sylvain Cote Wrote: Hello Monte,

I have created the following scenarios to clear up my (non?) understanding of the port assignment using PPLUG.
Please do the correction where they are needed.

Example 1 : one set of applications spent over 2 non-bank-switched images that will normally use one port on the back

location: the 2 images are at 0x840 and 0x841

expected: 0x840 at page 8 bank 0 & 0x841 at page 9 bank 0

command: "+840 8" PPLUG

Example 2 : one set of applications spent over 4 non-bank-switched images that will normally use two ports on the back

location: the 4 images are at 0x840, 0x841, 0x842 and 0x843

expected: 0x840 at page 8 bank 0, 0x841 at page 9 bank 0, 0x842 at page A bank 0 & 0x843 at page B bank 0

command: "%840 8" PPLUG

Example 3 : one set of applications spent over 2 bank-switched images that will normally use one half-port on the back

location: the 2 images are at 0x840, 0x841

expected: 0x840 at page 8 bank 0 & 0x841 at page 8 bank 1

command: "*840 8" PPLUG

Example 4 : one set of applications spent over 4 bank-switched images that will normally use one half-port on the back

location: the 4 images are at 0x840, 0x841, 0x842 and 0x843

expected: 0x840 at page 8 bank 0, 0x841 at page 8 bank 1, 0x842 at page 8 bank 2 & 0x843 at page 8 bank 3

command: "*840 8" PPLUG

Example 5 : two sets of applications spent over 7 bank-switched images that will normally use one port on the back

location 1: the app 1 has 3 images are at 0x840, 0x841 and 0x842

location 2: the app 2 has 4 images are at 0x843, 0x844, 0x845 and 0x846

expected 1: 0x840 at page 8 bank 0, 0x841 at page 8 bank 1 & 0x842 at page 8 bank 2

expected 2: 0x843 at page 9 bank 0, 0x844 at page 9 bank 1, 0x845 at page 9 bank 2 & 0x846 at page 9 bank 3
is it ?

command 1: "*840 8" PPLUG

command 2: "*843 9" PPLUG
or

command: "/840 8" PPLUG

Question for #5: how do you find how many images are part of the same image set ?

Thank you!

Best regards,

Sylvain

Examples 1, 2 and 4 are correct.

Example 3 is a subset of Example 4, and the two pages at 0x842 and 0x843 will still
be loaded, even though they are never referenced by the code at 0x840 and 0x841.

Example 5 is partially correct. When using two "*" types everything will work. But if
you want to use the "/" type, the second page needs to start at 0x844.

The type code tells the PPLUG exactly how the MMU should be programmed, and
the order and count is fixed. Recall that each page/bank combination has an MMU
entry that must be programmed. Using your example, with starting address 0x840,
this is how the MMU registers are programmed: (page/bank)

"-" : P1/B1 gets 0x840, P1/B2 gets 0x840, P1/B3 gets 0x840, P1/B4 gets 0x840

"+" : P1/B1 gets 0x840, P1/B2 gets 0x840, P1/B3 gets 0x840, P1/B4 gets 0x840
P2/B1 gets 0x841, P2/B2 gets 0x841, P2/B3 gets 0x841, P2/B4 gets 0x841

"$" : P1/B1 gets 0x840, P1/B2 gets 0x840, P1/B3 gets 0x840, P1/B4 gets 0x840
P2/B1 gets 0x841, P2/B2 gets 0x841, P2/B3 gets 0x841, P2/B4 gets 0x841
P3/B1 gets 0x842, P3/B2 gets 0x842, P3/B3 gets 0x842, P3/B4 gets 0x842

"%" : P1/B1 gets 0x840, P1/B2 gets 0x840, P1/B3 gets 0x840, P1/B4 gets 0x840
P2/B1 gets 0x841, P2/B2 gets 0x841, P2/B3 gets 0x841, P2/B4 gets 0x841
P3/B1 gets 0x842, P3/B2 gets 0x842, P3/B3 gets 0x842, P3/B4 gets 0x842
P4/B1 gets 0x843, P4/B2 gets 0x843, P4/B3 gets 0x843, P4/B4 gets 0x843

"+* : P1/B1 gets 0x840, P1/B2 gets 0x841, P1/B3 gets 0x842, P1/B4 gets 0x843

"/" : P1/B1 gets 0x840, P1/B2 gets 0x841, P1/B3 gets 0x842, P1/B4 gets 0x843
P2/B1 gets 0x844, P2/B2 gets 0x845, P2/B3 gets 0x846, P2/B4 gets 0x847

All of these options work with PPLUG, but only "-" and "*" work with PLUG, because
the partial-key code that I use for all prompting functions doesn't handle the
other keypresses.

Hope this clarifies things. I guess I need to expand the section in the manual.

Monte

Sylvain Cote · 07-25-2017, 06:31 PM

Hello Monte,

ok, I think I got it, please verify the following table to see if my understanding is correct.

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+

|       "-"        |        "+"       |        "$"       |        "%"       |       "*"        |        "/"       |

+------------------+------------------+------------------+------------------+------------------+------------------+

| P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 |

| P1/B2 gets 0x840 | P1/B2 gets 0x840 | P1/B2 gets 0x840 | P1/B2 gets 0x840 | P1/B2 gets 0x841 | P1/B2 gets 0x841 |

| P1/B3 gets 0x840 | P1/B3 gets 0x840 | P1/B3 gets 0x840 | P1/B3 gets 0x840 | P1/B3 gets 0x842 | P1/B3 gets 0x842 |

| P1/B4 gets 0x840 | P1/B4 gets 0x840 | P1/B4 gets 0x840 | P1/B4 gets 0x840 | P1/B4 gets 0x843 | P1/B4 gets 0x843 |

+------------------+------------------+------------------+------------------+------------------+------------------+

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+

|                  | P2/B1 gets 0x841 | P2/B1 gets 0x841 | P2/B1 gets 0x841 |                  | P2/B1 gets 0x844 |

|                  | P2/B2 gets 0x841 | P2/B2 gets 0x841 | P2/B2 gets 0x841 |                  | P2/B2 gets 0x845 |

|                  | P2/B3 gets 0x841 | P2/B3 gets 0x841 | P2/B3 gets 0x841 |                  | P2/B3 gets 0x846 |

|                  | P2/B4 gets 0x841 | P2/B4 gets 0x841 | P2/B4 gets 0x841 |                  | P2/B4 gets 0x847 |

+------------------+------------------+------------------+------------------+------------------+------------------+

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+

|                  |                  | P3/B1 gets 0x842 | P3/B1 gets 0x842 |                  |                  |

|                  |                  | P3/B2 gets 0x842 | P3/B2 gets 0x842 |                  |                  |

|                  |                  | P3/B3 gets 0x842 | P3/B3 gets 0x842 |                  |                  |

|                  |                  | P3/B4 gets 0x842 | P3/B4 gets 0x842 |                  |                  |

+------------------+------------------+------------------+------------------+------------------+------------------+

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+

|                  |                  |                  | P4/B1 gets 0x843 |                  |                  |

|                  |                  |                  | P4/B2 gets 0x843 |                  |                  |

|                  |                  |                  | P4/B3 gets 0x843 |                  |                  |

|                  |                  |                  | P4/B4 gets 0x843 |                  |                  |

+------------------+------------------+------------------+------------------+------------------+------------------+

Sylvain

Monte Dalrymple · 07-25-2017, 06:58 PM

(07-25-2017 06:31 PM)Sylvain Cote Wrote: Hello Monte,

ok, I think I got it, please verify the following table to see if my understanding is correct.

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+ |       "-"        |        "+"       |        "$"       |        "%"       |       "*"        |        "/"       | +------------------+------------------+------------------+------------------+------------------+------------------+ | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | P1/B1 gets 0x840 | | P1/B2 gets 0x840 | P1/B2 gets 0x840 | P1/B2 gets 0x840 | P1/B2 gets 0x840 | P1/B2 gets 0x841 | P1/B2 gets 0x841 | | P1/B3 gets 0x840 | P1/B3 gets 0x840 | P1/B3 gets 0x840 | P1/B3 gets 0x840 | P1/B3 gets 0x842 | P1/B3 gets 0x842 | | P1/B4 gets 0x840 | P1/B4 gets 0x840 | P1/B4 gets 0x840 | P1/B4 gets 0x840 | P1/B4 gets 0x843 | P1/B4 gets 0x843 | +------------------+------------------+------------------+------------------+------------------+------------------+

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+ |                  | P2/B1 gets 0x841 | P2/B1 gets 0x841 | P2/B1 gets 0x841 |                  | P2/B1 gets 0x844 | |                  | P2/B2 gets 0x841 | P2/B2 gets 0x841 | P2/B2 gets 0x841 |                  | P2/B2 gets 0x845 | |                  | P2/B3 gets 0x841 | P2/B3 gets 0x841 | P2/B3 gets 0x841 |                  | P2/B3 gets 0x846 | |                  | P2/B4 gets 0x841 | P2/B4 gets 0x841 | P2/B4 gets 0x841 |                  | P2/B4 gets 0x847 | +------------------+------------------+------------------+------------------+------------------+------------------+

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+ |                  |                  | P3/B1 gets 0x842 | P3/B1 gets 0x842 |                  |                  | |                  |                  | P3/B2 gets 0x842 | P3/B2 gets 0x842 |                  |                  | |                  |                  | P3/B3 gets 0x842 | P3/B3 gets 0x842 |                  |                  | |                  |                  | P3/B4 gets 0x842 | P3/B4 gets 0x842 |                  |                  | +------------------+------------------+------------------+------------------+------------------+------------------+

Code:

+------------------+------------------+------------------+------------------+------------------+------------------+ |                  |                  |                  | P4/B1 gets 0x843 |                  |                  | |                  |                  |                  | P4/B2 gets 0x843 |                  |                  | |                  |                  |                  | P4/B3 gets 0x843 |                  |                  | |                  |                  |                  | P4/B4 gets 0x843 |                  |                  | +------------------+------------------+------------------+------------------+------------------+------------------+

Sylvain

Looks correct.