Recreating Woodstock (67)

[Alejandro Paz(Germany)]

Hello,

like some of you know, I've been working on a re-implementation of the Woodstock class machines. I started with the 25 and later jumped to the 67. After several prototypes, I settled for a landscape layout similar to those of the voyagers. My preference, I wanted a development platform that reflected a bit more what I think is the best layout in terms of, I don't know, I just think they fit better in a cramped desk like mine ! .

I'm writing a logbook about the inner workings of my particular implementation, it is not bit serial it is nibble serial and the rom word is read at once. It doesn't make it any less difficult, I think.

I went with a Lattice MachXO2-7000ZE for low power, and while it is lower power than the 67, at 7 mA, it is in no way what I wanted, I was expecting uA level consumption. I'll have to explore other clocking mechanisms, I'm using the internal clock generator, to try to lower consumption. On-Off is something that I haven't researched well yet. The 67 turns completely off when... off ?... The others (voyagers) have built-in sleep mechanisms.
There are other alternatives like the iCE variants, nowadays there are like 5 families ! with very confusing names.... they should be a bit less hungry, and the 67 should fit in 1280 LUTs when the trace unit is not synthesized. But it needs 6 block rams for microcode and registers.

I'll re-post the code-base on github, I removed the old code as it is already two generations old, so to say. I re-wrote most of it a couple weeks ago.

In case someone asks: A replacement board for the 67 is something I thought about, I just do not want to use my only 67 as a ginny pig, it works flawlessly, well not so as the card reader never ever worked, not even in the old days (89-90).
I even got a replacement, damaged 71 after begging and more begging, and some dancing around a camp fire with a stone axe.... Maybe someone has a corroded one that could be lent for a brain surgery

[EdS2]

Sounds great - please link to github when you're ready.

[Alejandro Paz(Germany)]

I have been very busy as of lately but did find the time to post the design files as promised.

Woodstock on an FPGA

I have been thinking about slowing the clock to 32 kHz, using an external oscillator, they are low power, much lower than the internal oscillator of the MachXO2, and increasing the throughput of the CPU from say 18 clocks for a 14-nibble opcode down to 4 clocks. This was achieved using a parallel ALU instead of a nibble-wise one. Logic count did go up like quite a bit !:

Design Summary
Number of registers: 672 out of 7209 (9%)
PFU registers: 671 out of 6864 (10%)
PIO registers: 1 out of 345 (0%)
Number of SLICEs: 1671 out of 3432 (49%)
SLICEs as Logic/ROM: 1671 out of 3432 (49%)
SLICEs as RAM: 0 out of 2574 (0%)
SLICEs as Carry: 194 out of 3432 (6%)
Number of LUT4s: 3259 out of 6864 (47%)


I'm still working on it, it doesn't have display output yet.

[Harald]

(07-26-2017 08:02 AM)Alejandro Paz(Germany) Wrote:  I have been very busy as of lately but did find the time to post the design files as promised.

Woodstock on an FPGA

I have been thinking about slowing the clock to 32 kHz, using an external oscillator, they are low power, much lower than the internal oscillator of the MachXO2, and increasing the throughput of the CPU from say 18 clocks for a 14-nibble opcode down to 4 clocks. This was achieved using a parallel ALU instead of a nibble-wise one. Logic count did go up like quite a bit !:

Design Summary
Number of registers: 672 out of 7209 (9%)
PFU registers: 671 out of 6864 (10%)
PIO registers: 1 out of 345 (0%)
Number of SLICEs: 1671 out of 3432 (49%)
SLICEs as Logic/ROM: 1671 out of 3432 (49%)
SLICEs as RAM: 0 out of 2574 (0%)
SLICEs as Carry: 194 out of 3432 (6%)
Number of LUT4s: 3259 out of 6864 (47%)


I'm still working on it, it doesn't have display output yet.

Thanks for sharing!
Did you find a supplier for the metal domes for the keys? I would like to do something similar.

[Alejandro Paz(Germany)]

The metal domes, what I forgot to mention, I got them via aliexpress. There are a lot of different sizes, and kinds.

The ones I used are 9 mm in diameter. I'd say they are like the ones HP used, more or less.
9 mm metal dome, the ones I bought
I got bigger ones (because in aliexpress is sometimes difficult to size exactly what they are offering...) that have a pin, so you need a pad and two holes for the pins...
12 mm with pins

I also got 7 mm ones, they are a bit small, I think.
As you see the domes are held in place with tape, one side tape...

Something like this would probably also do:

8 mm cross metal dome

[PANAMATIK]

(07-26-2017 08:02 AM)Alejandro Paz(Germany) Wrote:  I have been very busy as of lately but did find the time to post the design files as promised.

Woodstock on an FPGA

I'm still working on it, it doesn't have display output yet.

Very nice FPGA solution. Running the FPGA with 32kHz using parallelism instead of original 720kHz is an achievement. Why is the display output missing, I can see numbers in your image.

If you need a decoder for the HP-67 display code, just ask.

Bernhard

[Alejandro Paz(Germany)]

iThanks for the offer ! you see the thing is not that I haven't written any display interpreter, it is a bit complexer:

The code I posted works at 520 kHz, it has display output, as one can see in the pictures, you can write programs, run programs and so on. I can send you a board too if you want. You need a DOGM132 (boght it at Reichelt) The FPGA and voltage regulator by Mouser and the metal domes as you saw above at aliexpress (sadly I bought only 100). I wanted a development platform for more models, nut and saturn based. Sadly for the small Saturn based there are no ROMs, so I am partially writing my own . Saturn code is very compact. All math routines fit in like 4 kBytes, amazing.

The 32 kHz development tree, so to say, misses display output because I haven't done it yet. I was more interested to see if I could get the processor running without impacting the "user interface" by trying to reach the minimum 3200 ops/s like the original 67. It runs at about 6000 ops/s, maybe a bit more, ifs are 6 clocks long.
This code hasn't been posted yet because it is not finished and would need another board:
A Text display instead of a graphics display and an external 32 kHz oscillator.

The refresh of the graphic display at 32 kHz would be a bit slow, I have to test it. A line needs 125 bytes at 32 kHz would need like 30 ms... it is doable, it runs in parallel anyways.
I got sidetracked rewriting the code in VHDL, and getting the tools up and running. I still like the liberty you get with verilog .